Semiconductor component having maximized bonding areas of electrically conductive members connected to semiconductor device and connected to leadframe and method of producing

ABSTRACT

A semiconductor component and method for producing. The semiconductor component includes a semiconductor device and a leadframe. A package layout is defined and the orientation of electrically conductive members with respect to the semiconductor device and inner contact areas of the leadframe is altered so as to maximize the interfacial bonding area. The constraints of the standard package dimensions and the component assembly method are taken into account.

CROSS-REFERENCE TO RELATED APPLICATIONS

This Utility Patent Application is a National Filing under 35 U.S.C. 371of International Application PCT/IB2005/002893, filed Sep. 27, 2005,incorporated herein by reference.

BACKGROUND

This disclosure relates to methods for increasing the current carryingcapacity of a semiconductor component and to semiconductor componentswith increased current carrying capacity.

High power semiconductor components such as diodes and transistors,e.g., MOS-FETs and IGBTs, are normally provided to the customer as apackaged semiconductor component. The packaged semiconductor component,typically, has one of a number of standard package outlines whichconforms to agreed industry standards regarding the outer form anddimensions of the plastic package as well as the number, dimensions andspacing of the pins. A standard package outline has the advantage thatthe component can be simply mounted on standardized printed circuitboards.

However, the packages suffer from the disadvantage that the currentcarrying capacity is limited. In order to increase the current carryingcapacity, it is known, for example from US 2003/0011051, to provide twoor more bonding wires which are connected in parallel between the powerelectrode of the semiconductor die and the source lead of thelead-frame.

The leadframe and package outline are also modified in order to furtherincrease the current carrying capacity. The pin sequence of the packageis changed in order to increase the size of the source post, or innercontact area of the source pin. Additionally, the cross-sectional areaof the external portions of the pins is increased to increase thecurrent carrying capacity of the package.

However, although the current carrying capacity may be increased bymodifying the package and pins, the advantages offered to the user of astandard package outline and a standard pin arrangement are lost. Theuser, therefore, has to modify the board in order to be able to mountthe modified package. This increases the complexity for the user andincreases the costs which can outweigh the benefit of a higher currentcarrying capacity.

For these and other reasons, there is a need for the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the present invention and are incorporated in andconstitute a part of this specification. The drawings illustrate theembodiments of the present invention and together with the descriptionserve to explain the principles of the invention. Other embodiments ofthe present invention and many of the intended advantages of the presentinvention will be readily appreciated as they become better understoodby reference to the following detailed description. The elements of thedrawings are not necessarily to scale relative to each other. Likereference numerals designate corresponding similar parts.

FIG. 1 illustrates a semiconductor component assembled after a firstiteration of the method of the invention.

FIG. 2 illustrates a semiconductor component assembled after a seconditeration of the method according to the invention is performed on thecomponent of FIG. 1.

FIG. 3 illustrates the assembly of a semiconductor component accordingto a second embodiment of the invention.

FIG. 4 illustrates the first position of the wire bond clamps whenassembling a semiconductor component according to a third embodiment ofthe invention.

FIG. 5 depicts the second position of the wire bond clamps whenassembling the semiconductor component of FIG. 4.

FIG. 6 illustrates the assembly a semiconductor component according to afourth embodiment of the invention.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to theaccompanying drawings, which form a part hereof, and in which isillustrated by way of illustration specific embodiments in which theinvention may be practiced. In this regard, directional terminology,such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc.,is used with reference to the orientation of the Figure(s) beingdescribed. Because components of embodiments of the present inventioncan be positioned in a number of different orientations, the directionalterminology is used for purposes of illustration and is in no waylimiting. It is to be understood that other embodiments may be utilizedand structural or logical changes may be made without departing from thescope of the present invention. The following detailed description,therefore, is not to be taken in a limiting sense, and the scope of thepresent invention is defined by the appended claims.

According to embodiments of the invention, a method for increasing thecurrent carrying capacity of a semiconductor component having a standardpackage outline and a standard pin arrangement includes the followingprocesses.

Firstly, a package layout is defined. The package layout includes a diepad having an edge defining a first line and lateral dimensions. Thepackage layout also includes a plurality of leads disposed on one sideof the die pad. Each lead has an inner portion and an outer portion. Atleast one drain lead extends from the die pad in a direction defining asecond line. The inner portion of each of the remaining leads includesan inner contact area which is spaced at a distance from the die pad.Each of the remaining leads extends in a direction parallel to thesecond line. The inner contact area of each remaining lead has maximumallowable dimensions. The package layout further includes asemiconductor device, which has lateral dimensions which are equal to orless than the lateral dimensions of the die pad, and a plurality ofelectrically conductive connecting members.

The area of the inner contact area is defined and the cross-sectionalarea of the electrically conductive connecting members is defined. Whenthe electrically conductive connecting member is bonded to a surface, aninterfacial bonding area is created between the electrically conductiveconnecting members and the surface. The interfacial bonding area of theelectrically conductive connecting members having the definedcross-sectional area after it is bonded to a surface is calculated. Thefollowing optimization method is then performed:

(a) a first end of the electrically conductive connecting member isorientated with respect to the second line to maximize the interfacialbonding area between the electrically conductive connecting member andthe inner contact area;

(b) a second end of the electrically conductive connecting member isorientated with respect to the first line to maximize the interfacialbonding area between the electrically conductive connecting member andthe upper surface of the semiconductor device;

(c) the semiconductor device is orientated with respect to the firstline so that the central portion of the electrically conductiveconnecting member has an orientation with respect to the edge of thesemiconductor device which is as close to 90° as possible and so thatthe semiconductor device remains within the area of the die pad;(d) the unoccupied area of the inner contact area is determined;(e) it is then determined if the unoccupied area is equal to or largerthan a predetermined value. The predetermined value is the area requiredby the bonding tool clamps, for example. If the unoccupied area is notequal to or larger than a predetermined value process (f) is performed.If the unoccupied area is equal to or larger than a predetermined valueprocess (g) is performed,(f) the relationship between the area of the inner contact area and thecross-sectional area of the electrically conductive connecting member ischanged by increasing the area of the inner contact area and/ordecreasing the cross-sectional area of the electrically conductiveconnecting means. The interfacial bonding area is calculated andprocesses (a) to (e) of the method are repeated;(g) it is then determined if the unoccupied area is larger than a secondpredetermined value. The second predetermined value defines anon-optimum interfacial area. If the unoccupied area is larger than thesecond predetermined value, the cross-sectional area of the electricallyconductive connecting member is increased, the interfacial bonding areais calculated and processes (a) to (e) are repeated. If the unoccupiedarea is not larger than a second predetermined value, the determinedvalues are output.

The values which may be determined by this method include: the area ofthe inner contact area; the cross-sectional area of the electricallyconductive connecting member; the orientation of the first end of theelectrically conductive member with respect to the second line; theorientation of the second end of the electrically conductive member withrespect to the first line, and the orientation of the semiconductordevice on the die pad. The interfacial bonding area and the unoccupiedarea of the inner contact area may also be output.

These values are used in the assembly of the semiconductor component inorder that the resulting component has an increased current carryingcapacity.

A semiconductor component may then be assembled by firstly providing alead frame in which the inner contact area has lateral dimensions and anarea as determined by the disclosed method.

The semiconductor device is then mounted on the die pad with anorientation with respect to the first line, defined by an edge of thedie pad, as determined by the method according to the invention.

The semiconductor device is electrically connected to the inner contactarea by electrically conductive connecting members having across-sectional area according to the disclosed method. The electricallyconductive connecting member is orientated with respect to thesemiconductor device and to the inner contact area as determined by themethod.

In a further process of the assembly, further electrical connections maybe provided between control contacts, such as the gate contact, and thelead frame. The semiconductor device, die pad, electrically conductiveconnecting members and the inner portions of the leads are thenencapsulated in a plastic molding compound. This is performed,typically, by a transfer molding process in which the mold provides thecomponent with a plastic housing mass with outer surfaces whichcorrespond to the desired standard package outline.

The disclosed method provides a method by which the current carryingcapacity of a semiconductor component may be increased withoutmodifications to the package outline or to the pin arrangement. Themethod provides a means by which the internal layout of the package isimproved, and may be optimized, so as to increase the current carryingcapacity.

In this context, the pin arrangement is used to denote the externalportions of the pins which are seen by the customer or user. The pinarrangement refers to the size of the individual pins, their spacingfrom each other and their arrangement with respect to the plasticpackage housing of the component.

This optimization of the internal layout of the package has the furtheradvantage that a semiconductor device with a particular current demandmay be accommodated in a component having a smaller package outline.This is particularly desirable as the miniaturization of microelectronicsystems without a loss in power or functionality is, in general, one ofthe driving forces behind developments in this technical field.

The method according to embodiments of the invention provides a methodby which the interfacial area between the semiconductor device and theelectrically conductive connecting means and between the inner contactarea of the lead of the leadframe and the electrically conductiveconnecting members is optimised within the confines of the standardpackage outline.

Therefore, the method also provides the maximum interfacial bonding areaallowable for an inner contact area which itself has maximum allowabledimensions due to the standard package outline. An increased interfacialbonding area reduces the resistance of the electrically conductiveconnecting means and enables a larger current to be carried.

Additionally, the method takes the assembly process into account. Theelectrically conductive connecting member is typically attached to thesemiconductor device and to the inner contact area using a bonding tool.For electrically conductive connecting members in the form of bondwires, this is performed by a wire bonder. The bonding tool, typically,has clamps which are in contact with the lead frame, and, in particular,the inner contact area during the bonding process. This preventsmovement of the leads and the lead frame during the bonding process.

The method provides a method by which the interfacial bonding area ismaximized while leaving sufficient area of unoccupied that the bondingtool can be placed on the inner contact area. The bonding process can,therefore, be reliably carried out.

The method also includes the feature that the electrically conductiveconnecting member is orientated with respect to the semiconductor deviceso that the central portion of the electrically conductive connectingmeans has an orientation which is as close to 90° as possible to theedge of the semiconductor device. This orientational relationshipincreases the interfacial bonding area and enables the length of theconnection to be reduced. This reduces the inductance of the wire whichfurther improves the functionality of the component. This feature of themethod also further improves the reliability of the bonding process aswell as the reliability of the electrical connection after it has beenformed.

Furthermore, the method also includes a process by which the orientationof the semiconductor device on the die pad is altered under theconstraint that the semiconductor device remains within the area of thedie pad. Therefore, the outline of the package is not changed. Thesemiconductor device is orientated with respect to the edge of the diepad so that the central portion of the electrically conductiveconnecting means has an orientation with respect to the edge of thesemiconductor device which is as close to 90° as possible. This reducesthe length of the electrically conducting connecting means which reducesresistive losses and increases the current carrying capacity of thecomponent.

In an embodiment, the cross-sectional area of the electricallyconductive connecting member is selected from a plurality of pre-definedvalues. This embodiment takes into account that electrically conductiveconnecting members, such as bond wires, are typically provided by amanufacturer which provides the material in a limited range of standardsizes. This material is cheaper than material made specifically for acustomer order. Therefore, this embodiment of the method allows for theoptimisation of standard sized electrically conductive connecting meanswithin the standard package housing. This optimises the current carryingcapacity of the component while keeping the cost of the component as lowas possible.

In an embodiment, the electrically conductive connecting member isprovided by a bond wire with an essentially circular cross-section. Inan alternative embodiment, the electrically conductive connecting memberis provided by a foil with an essentially rectangular cross-section.

In an embodiment, the first end of the electrically conductiveconnecting member is orientated approximately perpendicular to thesecond line. This arrangement maximizes the interfacial bonding areabetween the bond formed at the first end of the electrically conductiveconnecting member and the inner contact area. In a further embodiment,the second end of the electrically conductive connecting member isorientated approximately parallel to the first line. In this embodiment,the interfacial bonding area is maximized between the bond at the secondend of the electrically conductive connecting means and thesemiconductor device.

In a further embodiment, both the first end and the second end areorientated approximately perpendicular to the edge of the inner contactarea and semiconductor device respectively. The edge of the innercontact area is essentially parallel to the first line defined by theedge of the die pad and essentially perpendicular to the second linedefined by the drain lead. This type of bond is commonly referred to asan S bond.

In a further embodiment of the invention, the first predetermined valuedefining the unoccupied area of the inner contact area required by thebonding tool clamps is the area required by the bonding tool clamps in asingle pass bonding process.

In a single pass bonding process, all of the bonds connecting thesemiconductor device to the inner contact area are performed with thebonding tool clamps in one position. Two or more physically isolatedelectrically conductive connecting members may be connected in parallelbetween the semiconductor device and the inner contact area withoutrepositioning the bonding tool clamps. This embodiment has the advantagethat the provision of two or more electrically conductive connectingmembers connected in parallel further reduces the resistance of thecurrent carrying pass within the package outline. As all of the bondsare formed using one position of the bonding tool clamps, the bondingprocess can be carried out efficiently.

In an alternative embodiment, the first predetermined value defining theunoccupied area of the inner contact area required by the bonding toolclamps is the area required by the bonding tool clamps in a two passbonding process.

In a two pass bonding process, the bonding tool clamps are placed on theinner contact area and/or lead frame in a first position while a firstelectrically conductive connecting members is electrically connectedbetween the semiconductor device and the inner contact area. After thefirst electrically conductive connecting member is bonded, the bondingtool clamps are moved to a second position. A second electricallyconductive connecting member is then provided between the semiconductordevice and the inner contact area. The first and second electricallyconductive connecting members are connected in parallel between thesemiconductor device and the inner contact area so as to reduce theresistance of the current path.

A two pass bonding process has the advantage that the area of the innercontact, which will be later occupied by the second electricallyconductive connecting member, can be used by the bonding tool clampwhile attaching the first electrically conductive connecting members.This can provide a more reliable clamping of the bonding tool on thelead frame during the first pass.

In a further embodiment, it is also possible that the wire bonding toolclamps are outside of the inner contact area during the second pass,i.e. when the second electrically conductive conducting member isproduced between the semiconductor device and the inner contact area.This is possible due to the stability provided to the lead frame andinner contact area by the first electrically conductive connectingmember. This embodiment has the advantage that the area, which isunoccupied by the interfacial bonding areas, is reduced. Therefore, theinterfacial bonding area may be increased. This further reduces theresistance of the current path and can also enable the current carryingcapacity of the component to be increased.

Their further embodiment, the following additional processes may becarried out after process (d) of the optimization process outlinedabove.

The area required by each bonding tool clamp within the area of theinner contact area is defined and the lateral position of the bondingtool clamp within the area of the inner contact area is defined. Thelateral position of the unoccupied area of the inner contact area isdetermined. A comparison of the lateral position of the unoccupied areaand the defined lateral position of the bonding tool clamp and thedefined area required by the bonding tool clamp is carried out. If thedefined lateral position of the bonding tool clamp and the defined arearequired by the bonding tool clamp lie outside the lateral position ofthe unoccupied area, process (f) of the method described above isperformed. If the defined lateral position of the bonding tool clamp andthe defined area required by the bonding tool clamp lie within thelateral position of the unoccupied area process (g) of the methoddescribed above is performed.

This embodiment of the invention takes into account the lateral positionof each bonding clamp within the area of the inner contact area.Therefore, the different area requirements for a single pass and a twopass bonding process can be taken into account and the interfacialbonding area maximised accordingly.

The invention also provides a semiconductor component having a standardpackage outline and a standard pin arrangement which includes a die padhaving an edge defining a first line and having a lateral dimensions.The component also includes a plurality of leads disposed on one side ofthe die pad. Each lead has an inner portion and an outer portion. Atleast one drain lead extends from the die pad in a direction defining asecond line. The inner portion of each of the remaining leads includesan inner contact area which is spaced at a distance from the die pad.Each lead extends in a direction parallel to the second line. Thesemiconductor component also includes a semiconductor device havinglateral dimensions which are equal to or less than the lateraldimensions of the die pad and a plurality of electrically conductiveconnecting members. The standard package outline is a TO252 packageoutline and the electrically conductive connecting members include bondwires with a diameter of greater than approximately 350 μm.

The semiconductor component, therefore, includes bond wires with alarger diameter than can be conventionally used in component with aTO252 package outline. Therefore, the current carrying capacity of thecomponent can be increased by using the method of the invention tooptimise the internal layout of the component so that the diameter ofthe bond wires may be increased and the component can be reliablyassembled. In an embodiment, the component includes two bond wires witha diameter of 350 μm which stretch between the semiconductor device anda single inner contact pad. In this embodiment, the component also has aTO252 package outline.

In further embodiment, the component includes two or more bond wireswith a diameter of approximately 500 μm. The two or more bond wiresreach between the semiconductor device and a single inner contact area.The provision of two bond wires with a diameter of approximately 500 μmfurther increases the current carrying capacity of a component with aTO252 package outline.

In a further embodiment, the semiconductor device is orientated withrespect to the first line, defined by an edge of the die pad, by anangle θ, where 0°<θ<90°. The semiconductor device is orientated so thatthe angle formed between the central portion of the bond wire and theedge of the semiconductor device is as close to 90° as possible underthe constraint that the semiconductor device is located within thelateral dimensions of the die pad. The semiconductor device can bemounted inside the standard package outline which avoids modifying thestandard dimensions of the package.

As the angle formed between the central portion of the bond wires andthe edge of the semiconductor device is as close to 90° as possible, thelength of the bond wire between the semiconductor device and the innercontact area can be reduced and may be chosen to be as short aspossible. This reduces inductance and improves the functionality of thedevice. In addition, the heat dissipated by the component is reducedwhich further improves the functionality of the component, for examplethe switching speed of a transistor.

In an embodiment, the semiconductor device is a high power semiconductordevice. The high power semiconductor device may be a power switchingdevice such as a MOSFET, a IGBT, a BJT or a diode. The power switchingdevice may also be a vertical power device.

In the description, the semiconductor power switch is described ashaving at least one source electrode, at least one drain electrode andat least one gate electrode as is used for MOSFET switches. However,this nomenclature is not intended to limit the semiconductor powerswitch to a MOSFET. For other types of semiconductor power switch, thisnomenclature refers to the corresponding feature. For a BJT, gatecorresponds to base, source corresponds to emitter and drain correspondsto collector. For a IGBT, source corresponds to emitter and draincorresponds to collector.

In summary, embodiments of the invention provide a method by which thecurrent carrying capacity of a semiconductor component with a standardpackage outline and a standard pin arrangement can be increased. In oneembodiment of the invention, a semiconductor component is provided whichhas a TO252 outline, also known as a Dpak 3 package, which includes twobond wires with a diameter of 350 μm. The bond wires include aluminiumand provide two parallel electrical connections between the source innercontact area or source lead post and a semiconductor MOSFET device.

In a further embodiment, a component with a TO252 package outlineincludes two aluminium source leads connected in parallel between thesource contact of the semiconductor device and the inner contact area ofthe source lead which each have a diameter of 500 μm. The currentcarrying capacity of the package is increased to around 90 Amps.

Embodiments of the invention, therefore, provide a Dpak 3 package whichis suitable for applications requiring 90 Amps. In conventionalpackages, this capacity is provided only by Dpak5 packages which have 5pins and are much larger. The invention, therefore, provides a packagewithout redundant leads and removes the design constraints of the PCBlayout which arise as a result of the use of a Dpak5 package for theMOSFET device.

FIG. 1 illustrates a plan view of a semiconductor component 1 assembledafter a first iteration of the disclosed. The semiconductor component 1includes a semiconductor device 2, a lead frame 3 and a plastic housing4 having a TO252 package outline 5. The semiconductor device 2 is avertical MOSFET device. The upper surface of the MOSFET device includesa source contact 6 and a gate contact 7. The lower surface of the MOSFETdevice includes the drain contact 8 which cannot be seen in FIG. 1.

According to the method of an embodiment of the invention a packagelayout 100 is defined. The package layout was defined as conforming tothe TO252 standard. Therefore, in the illustrated embodiment, thelateral dimensions of the leadframe 3, including a die pad 9, thenumber, position and dimensions of the outer portions leads 10 and themaximum lateral dimensions of a semiconductor device which will fitwithin the lateral dimensions of the die pad 9 are defined by thisstandard.

In the package layout 100, the lead frame 3 includes a die pad 9, whichis essentially rectangular, and three leads, or pins 10 which arearranged adjacent the long side 17 of the die pad 9 which defines afirst line. The outer portion of each of the three leads 10 extends in adirection which is essentially perpendicular to the long edge 17 of therectangular die pad 9. Each lead 10 extends in a direction essentiallyparallel to each of the other leads 10 of the component 1. The directionof the leads defines a second line.

The central lead 11 extends from and is mechanically and electricallyconnected to the die pad 9 and provides the drain lead 11 of the package1. The lead 12 positioned to one side (the left in the orientation ofthe component illustrated in FIG. 1) of the drain lead 11 is the gatelead of the component 1. The lead 13 positioned on the opposite side (onthe right in the orientation of the component illustrated in FIG. 1) ofthe drain lead 11 is the source lead 13 of the semiconductor component1. The three leads 10 each include an inner portion and an outerportion. The three leads 10 are joined by support bar 14 which isdisposed approximately perpendicular to the three leads 10. The supportbar 14 holds the lead-frame 3 within a lead frame strip which includes aplurality of essentially identical lead-frames 3 arranged in rows andcolumns which are not illustrated in FIG. 1 for clarity. The support bar14 is removed after the component assembly process is complete toelectrically isolate the three leads 11, 12, and 13.

The inner portion of the gate lead 12 and the source lead 13 includes aninner bonding area or lead post 15. The inner contact areas 15 arepositioned at a short distance from the edge of the die pad 3 and are,therefore, not directly mechanically attached to, or electricallyconnected to, the die pad 9.

According to the method of the invention, an area is defined for theinner bonding area 15. This area is, in this embodiment of the inventiondefined as A. The inner bonding area 15 extends, in each case, inwardlytowards the central drain lead 11. The portion of the inner contact area15 adjacent to the edge 17 of the die pad 9 is essentially rectangular.The portion of the inner die pad 15 from which the source lead 13extends is approximately triangular. The form of the inner contact areas15 can be considered as a rectangle in which the corner adjacent thedrain lead 11 which faces away from the die pad 9 has been removed.

The gate electrode 7 positioned on the upper surface of thesemiconductor device 2 is connected to the inner contact area 15 of thegate lead 12 by a single gold bond wire 18 which has a diameter of 75μm.

According to the method of the invention, the cross-sectional area ofthe connecting means which electrically connect the source contact 6 tothe leadframe 3 is then defined. In this embodiment of the invention,the source electrode 6 is electrically connected to the inner contactarea 15 of the source lead 13 by two bond wires 19 and 20 which each hasa defined diameter of 350 μm.

The interfacial bonding area 21, which defines the area of the bondformed between the bond wires 19 and 20 and the upper surface of thesource contact 6 and the upper surface of the inner contact area 15 wascalculated. This can be done based on the known bond process parameterssuch temperature and pressure of the bond process for a bond wire with adiameter of 350 μm. The optimization method of the invention was thencarried out.

The first end 21 of each source bond wire 19, 20 was orientated withrespect to the inner contact area 15 so as to maximise the interfacialbonding area.

The second end 22 of each bond wire 19,20 was orientated with respect tothe edge of the die pad to maximise the interfacial bonding area betweenthe second end 22 of each bond wire 19,20 and the upper surface of thesemiconductor device 2. As can be seen in FIG. 1, the semiconductordevice 2 was orientated such that the bond wires 19, 20 form an angle of45° to the edge of the semiconductor chip.

The semiconductor device 2 is, in this embodiment of the invention, alsoessentially rectangular and is positioned approximately concentricallyon the rectangular die pad 9. Therefore, the long edge 16 of thesemiconductor device 2 lies in a plane which is essentially parallel tothe long edge 17 of the die pad 9. The angle between the long edge 16 ofthe semiconductor device 2 and the long edge 17 of the die pad 9 is,therefore, approximately 0°.

With the restrictions of the size of the semiconductor device andlateral dimensions of the inner contact area 15, according to thefurther conditions regarding the area required by the bonding toolclamps, an angle of 45° between the second end 22 of the bond wires 19,20 and the edge 16 of the semiconductor device 2 is as close as possibleto an angle of 90°.

As can be seen in FIG. 1, the area A of the inner contact area 15 isinsufficient to accommodate the bond wires 19, 20. Therefore, accordingto the method of the invention, the area of the inner contact area wasincreased to a value B and the optimisation method repeated. The resultof the second iteration of the optimisation method is illustrated inFIG. 2.

Features which are essentially the same as those illustrated in FIG. 1are indicated by the same reference number in the following Figures andare not necessarily described in detail again.

The semiconductor component of FIG. 2 differs from that of FIG. 1 inthat the inner contact areas 15 are rectangular and have a larger areathan the inner contact areas illustrated in FIG. 1. In the seconditeration, the interfacial bonding areas were maximised and theorientation of the semiconductor chip with respect to the bond wires 19,20 was chosen so as to provide an angle as close to 90° as possible.

A comparison of the area of the inner contact area 15 occupied by theinterfacial bonding areas 23 and the unoccupied area illustrates that aninner contact area with an area of B is sufficiently large toaccommodate two bond wires 19, 20 with a diameter of 350 μm within aTO252 package outline. Sufficient space also remains for the wirebonding clamps. The component as illustrated in FIG. 2, therefore,fulfils the criteria of the method of the invention.

After the semiconductor component 1 has been assembled according to themethod of the invention, the semiconductor device 2, the die pad 9, theinner portions of the leads 10 including the inner contact areas 15, andthe bond wires 18, 19, and 20 are encapsulated in a plastic moldmaterial 4. The outer surfaces of the mold material 4 provide the outersurfaces of the semiconductor component 1. The outline of the packageprovided by these outer surfaces is indicated in FIG. 1 by the dashedline 5. In this embodiment of the invention, the semiconductor component1 has a package outline 5 which corresponds to the dimensions of a TO252package outline.

The position of the bonding tool clamps used to assemble a componentaccording to various embodiments of the method according to theinvention, are illustrated in relation to FIGS. 3 to 6.

FIG. 3 illustrates the assembly of a semiconductor component 25according to a second embodiment of the invention and illustrates acomponent position 26 of a leadframe strip. The component position 26 isused to assemble a semiconductor component 25 with the TO252 packageoutline. Since FIGS. 3 to 6 illustrate the production method for thefabrication of the source wire bonds 19, 20, the package outline is notillustrated in the figures for clarity.

The semiconductor component 25, according to a second embodiment of theinvention, differs from the semiconductor component 1 depicted in FIG.2, in that the semiconductor device 27 has smaller lateral dimensionsthan the semiconductor device 2 of the first embodiment. The innercontact areas 15 have an area B as in the embodiment of FIG. 2.

The semiconductor device 27 is also a MOSFET device and its uppersurface includes a source contact 6 and a drain contact 7. The draincontact 8 is positioned on its rear surface and is electricallyconnected to the die pad 9 and, therefore, the drain lead 11. Thesemiconductor component 25 was also assembled according to the method ofthe invention.

Since the lateral dimensions of the semiconductor device 27 are smaller,the semiconductor device 27 is orientated on the die pad so that thelong edge 16 of the semiconductor device 27 lies at an angle of around20° to the long edge 17 of the die pad 9. The source contact 6 iselectrically connected to the inner contact that 15 of the source lead13 by two wires 19, 20. The inner contact area 15 has essentially thesame lateral dimensions as the inner contact area 15 illustrated in FIG.2. The two bond wires 19, 20 also include aluminium and have a diameterof approximately 350 μm.

The central portion 24 of the bond wires 19, 20 lies at an angle ofapproximately 85° to the long edge 16 of the semiconductor device 27.The semiconductor component 25 was assembled using an embodiment of themethod of the invention in which the position of the bonding tool clamps28, 29, and 30 required to form the two source wires 19, 20 in a singlebonding pass process, is taken into account. The position of the bondingtool clamps in indicated in the figures by rectangles.

As can be seen in FIG. 3, the bonding tool clamp 28 is positioned sothat it clamps the drain lead 11 and the bottom left hand corner of theessentially rectangular inner contact area 15 of the source lead 13. Thetwo remaining bonding tool clamps 29, 30 placed in contact with thesupport bar 14 either side of the source lead 13. This arrangementprovides a stable clamping of the lead frame 3 during the wire bondingprocess while also requiring that only a small area or the inner contactarea 15 is occupied by the clamp 28 and is unavailable for use by theinterfacial bonds 20.

The method according to the invention was used to determined an optimumcombination of the area and position required by the bonding clamp 28,the available area of the inner contact area 15, the diameter of thewires 19, 20 and orientation of the semiconductor device 27 on the diepad 9. This combination of features results in an increased currentcarrying capacity of the semiconductor component 25 within a TO252package outline. This package can carry up to 90 Amps.

FIGS. 4 and 5 illustrate two stages in a method according to a thirdembodiment of the invention for the assembly of a semiconductorcomponent 31 using a two-pass wire bonding method.

The semiconductor component 31 includes a MOSFET semiconductor device 27and the lead frame 3. The lead frame 3 includes a rectangular die pad 9and three leads 10 disposed on one of the long sides of the die pad 3.Similarly to the embodiments of FIGS. 1 and 2, the lead frame 3 of thesemiconductor component 31 includes a central drain lead 11, a gate lead12 and a source lead 13. The source lead 13 and the gate lead 12 includeinner contact areas 15. Each inner contact area 15 is essentiallyrectangular, has an area B and extends from the innermost end of theinner portion of the respective gate lead 12 and source lead 13 towardsthe central drain lead 11. The lateral dimensions of the inner contactarea 15 is approximately the same as in the embodiments illustrated inFIGS. 2 and 3.

The MOSFET device 27 is mounted with its rear surface on the uppersurface of the die pad 9 so that the long side 16 of the MOSFET device27 dies at an angle of approximately 20° to the long side 17 of the diepad 9. The gate electrode 7 is connected by a first bond wire 18 whichincludes gold and has a diameter of approximately 75 μm to the innercontact area 15 of the gate electrode 12.

The MOSFET device 27 will be electrically connected by two bond wireswhich reach between the source contact 6 and the inner contact area 15of the source lead 13.

In this embodiment of the invention, the wire bonding of the sourcecontact 6 to the source lead 13 occurs in two passes. In the firststage, illustrated in FIG. 4, the wire bonding tool clamps 32 and 33 arepositioned on the lead frame 3 so as to simplify the production of afirst bond wire 19 between the source electrode 6 and the inner contactarea 15 of the source lead 13. As can be seen in FIG. 4, a wire bondingclamp 32 is positioned towards one side (the right side for theorientation of the component illustrated in FIG. 4) of the inner contactarea 15 in approximately the lateral centre of the short side. A secondwire bonding clamp 33 is positioned on the support bar 14 to the rightof the source lead 13. This provides a stable clamping of the lead frame3 while leaving the majority of the inner contact area 15 (the centraland left hand regions for the orientation illustrated in FIG. 4)unoccupied so as to simplify the bonding of the first bond wire 19 tothe inner contact area 15.

The lead frame 3 represents a single component position of a leadframestrip having a plurality of similar component positions, which are notillustrated in the Figure for clarity. In the first pass of the wirebond, a first wire bond 19 is produced between the source contact 6 ofthe MOSFET device 27 and the inner contact area 15 of the source lead 13in each of the component positions. In the second pass of the wire bondtool over the lead frame strip, a second bond wire 20 will be producedin each of the component positions.

The production of the second bond wire 20 between the source electrode 6disposed on the upper surface of the MOSFET device 27 and the innercontact area 15 of the source lead 13 is illustrated in connection withFIG. 5.

As can be seen in FIG. 5, the second bond wire 20 extends form thesource electrode 6 to the inner contact area 15 in a direction which isessentially parallel to that of the first bond wire 19. Since the innercontact area 15 is already mechanically secured to the die pad via thefirst bond wire 19 and the mounted semiconductor device 27, thepositioning of a bond wire clamp on the inner contact area in the secondpass can be avoided. As can be seen in FIG. 4, the two clamps 32 and 33are positioned on the support bar 14 either side of the source lead 13.This arrangement maximises the area available for bonding within theinner contact area 15.

FIG. 6 illustrates a semiconductor component 35 assembled using a methodaccording to the invention.

Similarly to the embodiments illustrated in FIGS. 3, 4 and 5, thesemiconductor component 35 includes a MOSFET device 27 and a lead frame3 including a die pad 9 and three leads 10. The MOSFET device 27 isorientated on the die pad 9 so that the long side 16 of the MOSFETdevice 27 lies at an angle of approximately 20° to the long side 17 ofthe die pad 9. The inner contact areas 15 have an area B and dimensionsessentially the same as the embodiments of FIGS. 3, 4 and 5.

The embodiment of FIG. 6 differs from the embodiments of FIGS. 3 and 5in that the source electrode 6 is electrically connected to the innercontact area 15 of the source lead 13 by two bond wires 19, 20 whichinclude a kink or bend 36. The first end 21 of each of the source bondwires 19, is positioned so as to be approximately perpendicular to thelong side of the inner contact area 15 and approximately parallel to thedrain lead 11. The second end 22 of each of the source wires 19,20 ispositioned on the source contact 6 of the semiconductor device 27 so asto form an angle of approximately 85° with the long side 16 of theMOSFET device 27. Therefore, the central portion 24 of each of the bondwires 19, 20 lies at an angle of approximately 160° to the direction ofthe first end 21 of the bond wires 19, 20 which is attached to the innercontact area 15 of the source lead 13.

As can be seen in FIG. 6, this arrangement allows the interfacialbonding area 20 between the two source wires 19, 20 and inner contactarea 15 to have an approximately square or rectangular form. Thisenables bond wires with a larger diameter to be accommodated on an innercontact area with the same lateral dimensions as in the embodimentsillustrated in FIGS. 1, 2 and 4. In this embodiment, the bond wires 19,20 have a diameter of 500 μm.

Furthermore, the interfacial bonding areas 20 can be positioned towardsthe lateral centre of the inner contact area 15. This has the advantage,that regions of the inner contact area 15 towards the two short sidesremains unoccupied by the bond wires 19, 20. This enables the wire bondclampers 32 and 33 to be positioned so as to clamp the outer regions ofthe two short sides of the inner contact area 15. This arrangementprovides a more stable clamping of the inner contact area as the innercontact area is directly clamped by the two bond wire clamps 32, 33.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments illustrated and describedwithout departing from the scope of the present invention. Thisapplication is intended to cover any adaptations or variations of thespecific embodiments discussed herein. Therefore, it is intended thatthis invention be limited only by the claims and the equivalentsthereof.

1. A method for producing a semiconductor component, comprising:defining a package layout, the package layout including: a die padhaving an edge defining a first line and having lateral dimensions; aplurality of leads disposed on one side of the die pad, each lead havingan inner portion and an outer portion, wherein at least one drain leadextends from the die pad in a direction defining a second line and theinner portion of each of the remaining leads comprises an inner contactarea which is spaced at a distance from the die pad, each lead extendingin a direction parallel to the second line, the inner contact areahaving maximum allowable dimensions; a semiconductor device havinglateral dimensions which are equal to or less than the lateraldimensions of the die pad; and a plurality of electrically conductiveconnecting members, defining an area of the inner contact area; definingan area of the electrically conductive connecting members; orientating afirst end of the electrically conductive connecting members with respectto the second line to maximize an interfacial bonding area between theelectrically conductive connecting members and a surface of the innercontact area; orientating a second end of the electrically conductiveconnecting members with respect to the first line to maximize aninterfacial bonding area between the electrically conductive connectingmembers and an upper surface of the semiconductor device; orientatingthe semiconductor device with respect to the first line so that thecentral portions of the electrically conductive connecting members havean orientation with respect to an edge of the semiconductor device whichis as close to 90° as possible and so that the semiconductor deviceremains within the area of the die pad; determining an unoccupied areaof the inner contact area; if the unoccupied area is less than a firstpredetermined value, then changing the area of the inner contact areaand/or the cross-sectional area of the electrically conductiveconnecting members to increase the unoccupied area; if the unoccupiedarea is equal to or greater than the first predetermined value and ifthe unoccupied area is larger than a second predetermined value, thenincreasing the cross-sectional area of the electrically conductiveconnecting members; and if the unoccupied area is equal to or greaterthan the first predetermined value and if the unoccupied area is notlarger than the second predetermined value, then outputting determinedvalues of the area of the inner contact area and the cross sectionalarea of the electrically conductive conducting members.
 2. The method ofclaim 1, wherein the first predetermined value is an area required bybonding tool clamps.
 3. The method of claim 2, wherein the firstpredetermined value is the area required by the bonding tool clamps in asingle pass bonding process.
 4. The method of claim 2, wherein the firstpredetermined value is the area required by the bonding tool clamps in atwo pass bonding process.
 5. The method of claim 2, further comprising:defining an area required by the bonding tool clamp within the area ofthe inner contact area; defining a lateral position of the bonding toolclamp within the area of the inner contact area; determining a lateralposition of the unoccupied area of the inner contact area; comparing thelateral position of the unoccupied area with the defined lateralposition of the bonding tool clamp and the defined area required by thebonding tool clamp; if the defined lateral position of the bonding toolclamp and the defined area required by the bonding tool clamp liesoutside the lateral position of the unoccupied area, then changing thearea of the inner contact area and/or the cross-sectional area of theelectrically conductive connecting members; if the defined lateralposition of the bonding tool clamp and the defined area required by thebonding tool clamp lies within the lateral position of the unoccupiedarea, and if the unoccupied area is larger than the second predeterminedvalue, then increasing the cross-sectional area of the electricallyconductive connecting members; and if the defined lateral position ofthe bonding tool clamp and the defined area required by the bonding toolclamp lies within the lateral position of the unoccupied area, and ifthe unoccupied area is not larger than the second predetermined value,then outputting determined values of the area of the inner contact areaand the cross sectional area of the electrically conductive conductingmembers.
 6. The method of claim 1, wherein the second predeterminedvalue is a non-optimum interfacial area.
 7. The method of claim 1,further comprising repeating the method until the unoccupied area isequal to or greater than the first predetermined value and theunoccupied area is not larger than the second predetermined value. 8.The method of claim 1, wherein the cross-sectional area of theelectrically conductive connecting members is selected from a pluralityof pre-defined values.
 9. The method of claim 1, wherein theelectrically conductive connecting members are bond wires with anessentially circular cross-section.
 10. The method of claim 1, whereinthe electrically conductive connecting members are foils with anessentially rectangular cross-section.
 11. The method of claim 1,wherein the first end of the electrically conductive connecting membersis orientated approximately parallel to the second line.
 12. The methodof claim 1, wherein the second end of the electrically conductiveconnecting members is orientated approximately perpendicular to thefirst line.
 13. A semiconductor component having a TO252 packageoutline, comprising: a die pad having an edge defining a first line andhaving a lateral dimension; a plurality of leads disposed on one side ofthe die pad, each lead having an inner portion and an outer portion,wherein at least one drain lead extends from the die pad in a directiondefining a second line and the inner portion of each of the remainingleads comprises an inner contact area which is spaced at a distance fromthe die pad, each lead extending in a direction parallel to the secondline; a semiconductor device having lateral dimensions which are equalto or less than the lateral dimensions of the die pad, the semiconductordevice having a plurality of contacts, wherein the semiconductor deviceis orientated with respect to the first line by an angle θ, where0°<θ<90°; and a plurality of bond wires with a diameter of greater thanapproximately 350 μm connecting the contacts of the semiconductor deviceto the leads.
 14. The semiconductor component of claim 13, wherein thebond wires have a diameter of approximately 500 μm.
 15. Thesemiconductor component of claim 13, wherein the semiconductor device isorientated with respect to the first line so that a central portion ofthe bond wires has an orientation with respect to an edge of thesemiconductor device which is as close to 90° as possible and so thatthe semiconductor device remains within the area of the die pad.
 16. Thesemiconductor component of claim 13, wherein the semiconductor device isa high power semiconductor device.
 17. The semiconductor component ofclaim 13, comprising wherein the semiconductor device is a MOSFET, aIGBT, a BJT or a diode.